1. Field of the Invention
The present invention relates to an inspection apparatus for inspecting overlapping figures, a charged particle beam writing apparatus, and an extraction method for extracting overlapping figures. For example, it relates to an apparatus and method for inspecting an overlap of figures which is generated between two or more, or a plurality of, chip data defined in writing data used for electron beam writing, and to a writing apparatus in which the above system is installed.
2. Description of Related Art
The lithography technique that advances microscale semiconductor devices is extremely important as being the only process of forming patterns in semiconductor manufacturing processes. In recent years, with high integration of large-scale integrated circuits (LSI), critical dimensions required for semiconductor device circuits are shrinking year by year. In order to form a desired circuit pattern on semiconductor devices, a master pattern (also called a mask or a reticle) of high precision is required. The electron beam writing technique intrinsically having excellent resolution is used for producing such highly precise master patterns.
FIG. 29 is a schematic diagram showing operations of a variable-shaped electron beam (EB) type writing apparatus. As shown in the figure, the variable-shaped electron beam writing apparatus, including two aperture plates, operates as follows: A first aperture plate 410 has a rectangular opening or “hole” 411 for shaping an electron beam 330. This shape of the rectangular opening may also be a square, a rhombus, a rhomboid, etc. A second aperture plate 420 has a variable-shaped opening 421 for shaping the electron beam 330 that passed through the opening 411 into a desired rectangular shape. The electron beam 330 emitted from a charged particle source 430 and having passed through the opening 411 is deflected by a deflector to pass through a part of the variable-shaped opening 421 and thereby to irradiate a target workpiece or “sample” 340 mounted on a stage which continuously moves in one predetermined direction (e.g. X direction) during the writing or “drawing.” In other words, a rectangular shape formed as a result of passing through both the opening 411 and the variable-shaped opening 421 is written in the writing region of the target workpiece 340 on the stage. This method of forming a given shape by letting beams pass through both the opening 411 and the variable-shaped opening 421 is referred to as a variable shaped method.
When performing the electron beam writing, layout of a semiconductor integrated circuit is first designed, and then, layout data (design data), in which pattern layout is defined, is generated. Then, the layout data is converted into writing data which is adapted to the electron beam writing apparatus. A writing pattern to be written by the electron beam writing apparatus may be composed of a plurality of arranged chips. Chip data used as writing data of each chip is generally stored in separate files. The electron beam pattern writing apparatus inputs the chip data of each chip, reconstructs the chip data to be one chip by merging performed at the position where chips are virtually arranged in the writing region, and writes the reconstructed writing pattern onto the target workpiece.
At this point, if writing is performed in the state that there is an overlap between the arranged figures, it results in a multiple exposure. Therefore, it is necessary to remove such an overlap between the figures beforehand.
FIG. 30 shows an example of the case of an overlap occurring between the figures in one chip. FIG. 30 shows the state in which a part of figures 502 and 504 in a certain region 500 in a chip A are overlapped with each other. Such an overlap can be removed by the fracture processing etc. when generating writing data. Therefore, before inputting writing data into a pattern writing apparatus, such an overlap between figures can be removed in advance. On the other hand, there is a case of an overlap occurring between figures in different chips.
FIG. 31 shows an example of an overlap between figures in different chips. In FIG. 31, figures 512, 514, and 516 are arranged in a certain region 510 in Chip B and figures 522, 524, and 526 are arranged in a certain region 520 in Chip C. In FIG. 31, the chips B and C are arranged in the writing region to be in such a manner that a part of the region 510 of Chip B and the region 520 of Chip C are overlapped with each other. In this case, as shown in FIG. 31, the figure 512 in Chip B and the figure 522 in Chip C may be partially overlapped with each other. In FIG. 31, the overlapped portion is shown in diagonal lines. Conventionally, an effective method to find such an overlap of figures between chips, which is produced when different chips are overlappingly arranged, has not been established. Therefore, when such an overlap of figures between chips occurs, it is not until the writing data is input into the pattern writing apparatus and a plurality of data conversions are performed to generate shot data that the multiple exposure is found. For example, it is not until the stage of checking a beam irradiation amount that the multiple exposure is found. However, even if the multiple exposure is found at this point, the following problems will still occur.
FIG. 32 shows an example of an overlap between figures when merging different chips. In FIG. 32, since the merging is performed at the position where Chips B and C are virtually arranged in the writing region, the figures 512, 514, 516, 522, 524 and 526 are allocated in a merged region 530. That is, at the stage of checking the amount of beam irradiation mentioned above, merging has already been finished. Thus, since the hierarchical structure of chips has already been reconstructed at the stage after merging, even if the overlapped figures 512 and 522 are found after the merging, there is a problem in that great time and effort is needed for investigating in which hierarchical region of which chip each of the figures was allocated.
As to the technique of removing overlapping in order to avoid a double exposure, the following is disclosed in a reference: in the case that a cell repeatedly allocated serves as a character pattern, if another character pattern adjacent to the cell exits, an associated overlap is investigated and an overlapped pattern is not shot, thereby not generating EB shot data (refer to, e.g., Japanese Patent Application Laid-open (JP-A) No. 2005-268657 [0025]). However, the reference concerned is not related to the case of allocating different chips. Thus, no method for inspecting an overlap between figures in the case of different chips being allocated is disclosed or suggested at all.
As mentioned above, when there is an overlap of figures between different chips, an effective method for investigating in which hierarchical region of which chip the figure was allocated before merging has not been established. Therefore, even if overlapped figures are found after merging, there exists a problem that it needs great time and effort to investigate in which hierarchical regions of which chips the figures were allocated.